The following description relates to an integrated circuit having a a memory cell array including a plurality of memory cells. Moreover, the description refers to a method of forming such an integrated circuit having a memory cell array.
Memory cells of a dynamic random access memory (DRAM) generally include a storage capacitor for storing an electrical charge which represents information to be stored and an access transistor connected with the storage capacitor.
In currently-used DRAM memory cells the storage capacitor can be implemented as a trench capacitor in which the two capacitor electrodes are disposed in a trench which extends into the substrate in a direction perpendicular to the substrate surface. According to another implementation of a DRAM memory cell the electrical charge is stored in a stacked capacitor, which is formed above the surface of the substrate.
For these and other reasons, there is a need for the present invention.